International Journal of Research in Computer Applications and Robotics

In digital VLSI system the clock distribution network and flip flops are most power consuming components. The reduction of power consumption by clock distribution networks & flip flop makes the total VLSI system as low power VLSI system. In the earlier VLSI system design, different power consumption methods are followed to design the various flip-flops .The SABFF(sense amplifier based flip flop) is one of the types of flip flops in digital VLSI system. The SABFF consists of pulse generator, sensing stage(frontend),latching stage(backend).In previous sense amplifier based flip flops, the sensing stage(frontend) is focused more to make the flip flop as low power consuming element. The proposed work is to design power efficient sense amplifier based flip flop by focusing the sensing stage. The various analyses on the sense amplifier based flip flop is carried out by changing the different sensing stages such as Current mirror sense amplifier (Ct mirror), Full latch sense amplifier.